A wide variety of electrical and electronic digital appliances require multiple internal clocks to synchronize and/or control internal processes. One exemplary appliance is a hard disk drive providing random access storage and retrieval of blocks of user data typically used by a host computing system. Within a disk drive, one clock may be provided to control operation of a microprocessor functioning as an embedded disk drive controller. Another clock may be used to regulate disk spindle speed. Yet another clock may be needed to control data transfer operations into and out of a cache buffer memory array. (In this regard, the clocking situation may be further complicated by the use of dynamic random access memory (DRAM) which requires periodic refreshing at a controlled refresh rate which may be slower than the actual data transfer rate). Yet another clock may be used for asynchronous peak detection of embedded servo information. One more clock may be needed to regulate data transfer rate between the disk drive and the host computer via a disk-host interface bus structure.
While a series of clocks are needed for proper functioning of the various processes, disk drive designs are undergoing on-going reductions in size and cost. A large scale integration of drive functions into one or a few application-specific integrated circuit (ASIC) semiconductor chips means that fewer and fewer external components, such as crystals, or crystal oscillator modules can be tolerated in size and cost reduced disk drive designs. Also, as data transfer rates continue to escalate, to rates as high as 40 to 100 Megabits or higher, onboard crystal oscillator circuits are increasingly difficult to realize with ASIC technology, with an undesired consequence that coveted circuit board space has been taken up with outboard, encapsulated, self contained oscillator modules available only at increased cost.
There have been prior approaches seeking to realize multiple clock generation within a single ASIC, based upon a stable reference crystal oscillator. However, those approaches have been complicated. One example is provided by U.S. Pat. No. 4,998,075 to Patton III, et al., entitled: "Programmable Multiple Oscillator Circuit". That patent described an arrangement in which a stored program included a value corresponding to each desired frequency. This value was compared with an actual value derived from each output frequency and used to adjust a voltage controlled oscillator providing the frequency.
Digital ring oscillators are known in the art. A ring oscillator may be formed of an interconnected ring of digital gates which includes therewithin at least one inverter gate, and sometimes, an odd number of inverter gates within the ring. A ring oscillator circuit has frequently been included within an ASIC as a test circuit in order to measure gate signal propagation delays of the particular ASIC design and/or layout, or to calibrate gate delays of signals propagating through the ASIC. Since ring oscillator test circuits are known ways to measure gate delays, they have been employed for that purpose in the prior art.
One prior example of an adjustable ring oscillator circuit for measuring the delay period of a delay circuit is described in U.S. Pat. No. 5,087,842 to Pulsipher et al., entitled: "Delay Circuit Having One of a Plurality of Delay Lines Which May Be Selected to Provide An Operation of a Ring Oscillator". The goal of the circuit described in that patent is to provide a controlled or calibrated delay line. It uses a ring oscillator circuit to determine actual delay of its own delay line. Once the actual delay of the oscillator ring is known, another delay line is adjusted by a crystal controlled microprocessor via a digital to analog converter. The FIG. 4 embodiment thereof suggests that delay line adjustment could be carried out by selecting delay taps via an 8 to 1 multiplexer.
Another example of a prior ring oscillator is described in U.S. Pat. No. 5,048,811 to Lewis, entitled: "Tuned Ring Oscillator". This patent is assigned to a disk drive manufacturer and describes a disk drive spindle frequency monitoring arrangement in which an adjustable ring oscillator is adjusted to the frequency of a disk spindle rotation signal, such as a once-per-revolution disk index signal. The described delay line architecture includes a series of transmission gates which requires as many control signals as there are taps.
A further example of a prior ring oscillator circuit is described in U.S. Pat. No. 5,241,429 to Holsinger, entitled: "Adaptive Prewrite Compensation Apparatus and Method". This patent, also assigned to the same disk drive manufacturer, describes a prewrite compensation circuit which is calibrated with the aid of a ring oscillator circuit structure formed within the same ASIC as also includes the prewrite compensation circuitry.
Other examples of digital ring oscillator circuits are found in U.S. Pat. No. 5,136,200 to Yousefi-Elezei, entitled: "PLL Clock Synthesizer Using Current Controlled Ring Oscillator"; U.S. Pat. No. 4,517,532 to Neidorff, entitled: "Programmable Ring Oscillator"; U.S. Pat. No. 4,884,041 to Walker, entitled: "Fully Integrated High-Speed Voltage Controlled Ring Oscillator"; U.S. Pat. No. 5,126,692 to Shearer et al., entitled: "Variable Frequency System Having Linear Combination of Charbe Pump and Voltage Controlled Oscillator"; U.S. Pat. No. 5,191,301 to Mullgrav, Jr., entitled: "Integrated Differential Voltage Controlled Ring Oscillator"; and, U.S. Pat. No. 5,208,557 to Kerrsh, III, entitled: "Multiple Frequency Ring Oscillator".
While ring oscillator circuits are generally understood, their performance is subject to at least three significant ASIC tolerances: power supply voltage fluctuations, ASIC temperature variations, and ASIC process variations from chip to chip. Because of these variations, ring oscillators have generally been deemed overly unstable and subject to frequency drift to be used as clocks for timing, controlling or regulating circuit processes and events.
Thus, a hitherto unsolved need has remained for an adjustable ring oscillator circuit for use within an ASIC for providing one of a plurality of frequency-regulated clocking signals for a digital electronics appliance, such as a hard disk drive, which may be readily adjusted in order to maintain a regulated frequency while in operation without glitches or interrupting oscillation, in order to compensate for frequency drift otherwise resulting from voltage, temperature, and/or process variations.